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dspddc_R12p1
- 基于DSPbuilder搭建的DDC，里面包括CIC滤波器，FIR低通滤波器，HB半带滤波器，NCO等，实现了GC5016芯片的功能-DSPbuilder erected based on DDC, which include the CIC filter, FIR low-pass filter, HB half-band filter, NCO, etc. to achieve the function of the GC5016 chip
serialports2
- 使用verilog以及VHDL编写的将串口数据转换为32位并口数据，作为FPGA和DSP接口使用（DSP型号：6205）-Use verilog and VHDL will be prepared by a 32-bit serial data into parallel data, as the FPGA, and DSP interface (DSP Model: 6205)
test
- xilinx ise6.3编译环境，verilog控制程序。实现对外部ad转换数据自动采集计算，并发送到DSP最后处理-xilinx ise6.3 build environment, verilog control procedures. To achieve automatic data acquisition external ad converter calculated and sent to final processing DSP
ADSP2100
- ADSP2100的Verilog源代码，可综合。ADSP2100是用的相当广泛的3款DSP架构之一，现在不太流行了，不过其架构相当精巧，和现在的处理器风格迥异，有兴趣的朋友可以看一下。-ADSP2100 the Verilog source code can be integrated. ADSP2100 is used in a wide range of 3, one of DSP architecture, it is less popular, but its structure rat
tst_saa7113h
- 飞利浦的视频解码芯片SAA7113H的Verilog控制源代码，该源代码加入了SRAM和DSP，很值得参考-The Verilog control code of Philips video decoder chip SAA7113H , the source code combine the interface of SRAM and DSP, it is worth considering
RS2322
- verilog 功能：DSP或单片机向FPGA的DPRAM中写入一块数据（最大不超过2K字节,前2个字节为代发送数据长度），然后给出启动信号send_start，本模块自动读出DPRAM中的数据，按设定的波特率将DPRAM中规定的长度的数据发送出去。 接口信号说明： send_start：启动FPGA串行发送脉冲 sys_rst：系统复位脉冲 bps_setup：波特率选择 clk5_714：5.714MHz时钟 char_in：从DPRAM中读出的代发送数据 R
mulx
- FPGA verilog乘法器 设计 用FPGA中DSP模块实现-FPGA verilog mulx
Robust and Optimal Control by Kemin Zhou
- Embeded-SCM Develop ARM-PowerPC-ColdFire-MIPS Embeded Linux SCM VxWorks uCOS DSP program Windows CE VHDL-FPGA-Verilog Other Embeded program
asic_final
- Verilog 程序 实现一个简单的语音信号增强DSP设计 分为左右声道-To realize a sound de-nosing dsp using verilog
a_vhd_16550_uart_latest.tar
- vhdl-fpga-c++-c-wireless networks-linux-verilog-cpld-arm-dsp
echo_dj
- verilog写的回波抵消程序，相当于写了个回波抵消的芯片，不是dsp，可编译后下载于FPGA,绝对原创，写了很长时间。-Verilog echo canceller written procedures, wrote the equivalent of echo canceller chip, not dsp, can be downloaded from the compiled FPGA, absolute originality, writing for a long time. -
dspafpga
- dsp与fpga通信的verilog程序，强烈推荐欢迎参考-dsp and fpga verilog communication program, it is strongly recommended to welcome reference
myuart
- 使用verilog语言编写的异步串口模块，带有16级深的FIFO，它与DSP28335的SCI相似，可以帮助初学者更快地理解FPGA和DSP的硬件结构和编程思路-Use verilog language of asynchronous serial port module, FIFO with deep level 16, it was similar with DSP28335 SCI, can help beginners to understand faster the FPGA and
zixiechengxu
- 用verilog编写的包含有与DSP通信，三电平svpwm实现的程序，-Written in verilog contains communicate with the DSP, three-level svpwm realize the procedures
exercise3
- 用verilog实现dsp与Fpga接口的同步设计，其功能包括读写操作及四个功能模块，采用两个fifo实现不同时钟域的地址与数据的转换，在quartus ii11.0环境下运行，运行此程序之前需运行将调用fifo。-Dsp using verilog achieve synchronization with Fpga interface design, its features include read and write operations and four functional modul
emif_tt
- 实现dsp与fpga的emif的verilog异步实现，可实现异步读写以及相应功能模块控制，文件中包含仿真后的波形图形以及仿真测试程序，运行环境quartus ii11.0，仿真环境mmodelsim se 6.5d-Achieve dsp and fpga verilog asynchronous implementation of the emif, enabling asynchronous reading and writing as well as the corresponding
fpga_ver
- Altera StratixII FPGA与DSP TS201实现总线通信的程序，Verilog实现-Altera StratixII FPGA and DSP TS201 implement the bus communication procedures, Verilog realization
echo_dj
- verilog写的回波抵消程序，相当于写了个回波抵消的芯片，不是dsp，可编译后下载于FPGA,绝对原创，写了很长时间。-Verilog echo canceller written procedures, wrote the equivalent of echo canceller chip, not dsp, can be downloaded from the compiled FPGA, absolute originality, writing for a long time.
echo_dj
- verilog写的回波抵消程序，相当于写了个回波抵消的芯片，不是dsp，可编译后下载于FPGA,绝对原创，写了很长时间。-Verilog echo canceller written procedures, wrote the equivalent of echo canceller chip, not dsp, can be downloaded from the compiled FPGA, absolute originality, writing for a long time.
hpi
- 实现FPGA控制DSP的HPI接口，使用verilog接口-Achieve FPGA DSP HPI interface control, use verilog interface